nvd
Full Member level 2
- Joined
- Jan 17, 2005
- Messages
- 129
- Helped
- 2
- Reputation
- 4
- Reaction score
- 2
- Trophy points
- 1,298
- Location
- Solar System
- Activity points
- 1,219
You may metal route over poly caps (if you don't fear accuracy/matching problems). DRC will always tell you, what's not allowed.nvd said:... I have heard that routing over poly capacitors is not allowed.
Are you sure with across? This certainly isn't allowed and would produce DRC errors. But you probably think of around? This would be ok, incl. its connection to gnd (for a p+ guard ring).nvd said:Secondly, I have guard rings across the poly capacitors. In some capacitors, I have connected them to the gnd in the layout to provide shielding. Is there any rule for it.
dick_freebird said:This would be foundry / design-kit specific problem, not Cadence.
The LVS tool should probe & zoom to individual errors so you can
dope it out. In doing so you will begin to understand what the
sometimes-peculiar error messages really mean.
Your schematic may have to represent the connections to
"guard ring" by whatever it extracts to. Try working with
a very small simple layout, where you can see the oddball that
might appear in the layout extracted view, so you can learn
how to represent the excess layout features for clean LVS.
I don't think this will help: You usually have a lot of p+ guard rings connected to gnd! (and n+ guard rings connected to vdd!) without needing a counterpart in schematics.nvd said:I may remove the ground connections to the ring in the layout and then check again.
AFAIK "gnd!" and "vdd!" are predefined nets in C@dence, but also "agnd!" & "avdd!", "dgnd!" & "dvdd!" can be used. The bang (!) just marks a global net.nvd said:... But why don't I get errors for "vdd". I haven't renamed it to "vdd!". Are these nets already defined?
This of course is always possible by separating the areas with (several) guard ring(s). Some foundries even allow for real electrical separation, but this needs a special process option (and a supporting PDK, of course).nvd said:I was also thinking of isolating the analog ground from the digital one.
Very good! Is useful, and the layout looks better! ;-)nvd said:I am implementing a sigma delta ADC (3-bit) and the 8-3 encoder may introduce switching noise although I am using decoupling capacitors in the free chip area.
No. You have to connect them: p+ on substrate to gnd! , n+ in n-well to vdd, by metal ! Didn't the DRC throw "floating well" error messages on you? If not, your PDK will arrange for these connections. Guard rings without the right potential connections are not efficient, in contrary: they could make things worse, even corrupt your chip!nvd said:What about the guard rings? They are not connected in the layout. Is this done at the manufacturing phase?
I don't think so, as you seem to have no pb. with "vdd" (up to the pad, hopefully!).nvd said:I have "vdd" and not "vdd!". Is it problematic for the capacitors?
n+ on n-well taps must be connected to vdd (or vdd!).nvd said:I don't see any another connection in the guard ring to connect to vdd!.
Just warnings, don't worry.nvd said:I am also getting ERC warnings of gates connected to vdd! or gnd!
?? Sounds dangerous. Latch-up can kill the chip.nvd said:... and some latch ups.
nvd said:Oh really!
I will let you know about the exact warning.
I am getting this warning because of interdigitization of transistors in OTA.
nvd said:I am also getting ERC warnings of gates connected to vdd! or gnd!
Thinking twice, I remember some foundries don't allow direct connection of gates to the global power supply rails, because their ESD protection might not be sufficient to protect gate inputs. In this case, 3 different types of connection are recommended:erikl said:Just warnings, don't worry.
erikl said:[
- extra vdd_ESD & gnd_ESD rails with standard gate protection (series resistor + 2 protection diodes to gnd! & vdd!)
It will, as deepak told you above. Normally, this should already be checked by DRC rules.nvd said:... There should be one contact within 20 µm of each point inside a transistor (preferably a lot of substrate contacts).
Let's hope, it fixes the problem.
No via. By contact to metal1 of course!nvd said:Can you tell me how can I connect vdd! to guard rings of the capacitors?
I mean which via to use?
Sorry, I can't believe it!I am well experienced with layout.
You mus b having metal 1 in your guardring instance..You can connect it to vdd! .nvd said:I am getting 1 ring (METAL1) across the capacitor which has been connected to gnd!
Your answer for vdd! connection to the ring is still not clear to me.
vdd for ntap , gnd ! for ptap...nvd said:Is it either gnd! or vdd! or both connections at the same time to the ring?
I doubt .... without proper biasing guarding will be of no use as they will not collect the carriers ( majority as well as minority ) .Still I am open for any views on this point.nvd said:Connections to vdd! and gnd! can be ignored according to the supervisor.
Connections to vdd! and gnd! can be ignored according to the supervisor.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?