Cadence Poly Capacitor

[nvd]

I am having problems with the final layout of my chip. In the case of individual blocks, I am not getting any errors from DRC and LVS. At LVS of the chip, I get errors regarding more gnd connection in the layout rather than in the schematic. I have heard that routing over poly capacitors is not allowed. I am using AMS (0.35 um) technology.

Secondly, I have guard rings across the poly capacitors. In some capacitors, I have connected them to the gnd in the layout to provide shielding. Is there any rule for it.

 

[erikl]

... I have heard that routing over poly capacitors is not allowed.

You may metal route over poly caps (if you don't fear accuracy/matching problems). DRC will always tell you, what's not allowed.

Secondly, I have guard rings across the poly capacitors. In some capacitors, I have connected them to the gnd in the layout to provide shielding. Is there any rule for it.

Are you sure with across? This certainly isn't allowed and would produce DRC errors. But you probably think of around? This would be ok, incl. its connection to gnd (for a p+ guard ring).

 

[dick_freebird]

This would be foundry / design-kit specific problem, not Cadence.

The LVS tool should probe & zoom to individual errors so you can
dope it out. In doing so you will begin to understand what the
sometimes-peculiar error messages really mean.

Your schematic may have to represent the connections to
"guard ring" by whatever it extracts to. Try working with
a very small simple layout, where you can see the oddball that
might appear in the layout extracted view, so you can learn
how to represent the excess layout features for clean LVS.

 

[nvd]

This would be foundry / design-kit specific problem, not Cadence.

The LVS tool should probe & zoom to individual errors so you can
dope it out. In doing so you will begin to understand what the
sometimes-peculiar error messages really mean.

Your schematic may have to represent the connections to
"guard ring" by whatever it extracts to. Try working with
a very small simple layout, where you can see the oddball that
might appear in the layout extracted view, so you can learn
how to represent the excess layout features for clean LVS.

I am well experienced with layout. So, I assume that I am not doing any layman mistake. As you suggested, the schematic may have to represent the "guard ring" connection. But I have no idea, how to modify the schematic of the poly capacitor to indicate this.

Probing and zooming is not working as everything matches (nets, pins, devices etc). The only mismatch is the number of connections which the ground pin makes in the layout is greater. I may remove the ground connections to the ring in the layout and then check again.

Regards.

Added after 2 minutes:

But you probably think of around? This would be ok, incl. its connection to gnd (for a p+ guard ring)[/quote]


Yes it is around the capacitor.

 

[erikl]

I may remove the ground connections to the ring in the layout and then check again.

I don't think this will help: You usually have a lot of p+ guard rings connected to gnd! (and n+ guard rings connected to vdd!) without needing a counterpart in schematics.

Did you run an ERC on schematics? If not, may be the connection between gnd and gnd! is missing in your schematic? A previous ERC run probably would have told you this. In layout, this connection could be default. (Just a guess. Please tell us, if you find the real reason!).
Rgds, erikl

 

[nvd]

Yes this was the problem. I checked the LVS result and it was complaining about a short between "gnd" and "gnd!". I read your post later on. I renamed the "gnd" pin in the schematic and the symbol to "gnd!". LVS match is ok now. But why don't I get errors for "vdd". I haven't renamed it to "vdd!". Are these nets already defined? I was also thinking of isolating the analog ground from the digital one. I am implementing a sigma delta ADC (3-bit) and the 8-3 encoder may introduce switching noise although I am using decoupling capacitors in the free chip area.

What about the guard rings? They are not connected in the layout. Is this done at the manufacturing phase? I have "vdd" and not "vdd!". Is it problematic for the capacitors?

Regards.[/quote]

 

[erikl]

... But why don't I get errors for "vdd". I haven't renamed it to "vdd!". Are these nets already defined?

AFAIK "gnd!" and "vdd!" are predefined nets in C@dence, but also "agnd!" & "avdd!", "dgnd!" & "dvdd!" can be used. The bang (!) just marks a global net.
I don't know why your pb. didn't appear with the "vdd" net. (Perhaps you were just lucky? ;-) )

I was also thinking of isolating the analog ground from the digital one.

This of course is always possible by separating the areas with (several) guard ring(s). Some foundries even allow for real electrical separation, but this needs a special process option (and a supporting PDK, of course).

I am implementing a sigma delta ADC (3-bit) and the 8-3 encoder may introduce switching noise although I am using decoupling capacitors in the free chip area.

Very good! Is useful, and the layout looks better! ;-)

What about the guard rings? They are not connected in the layout. Is this done at the manufacturing phase?

No. You have to connect them: p+ on substrate to gnd! , n+ in n-well to vdd, by metal ! Didn't the DRC throw "floating well" error messages on you? If not, your PDK will arrange for these connections. Guard rings without the right potential connections are not efficient, in contrary: they could make things worse, even corrupt your chip!

I have "vdd" and not "vdd!". Is it problematic for the capacitors?

I don't think so, as you seem to have no pb. with "vdd" (up to the pad, hopefully!).

Good luck! erikl

 

[nvd]

I am done with the layout of the whole chip. I just connected the METAL1 of the guard ring to gnd!. I don't see any another connection in the guard ring to connect to vdd!.

I am also getting ERC warnings of gates connected to vdd! or gnd! and some latch ups.

Regards.

 

[erikl]

I don't see any another connection in the guard ring to connect to vdd!.

n+ on n-well taps must be connected to vdd (or vdd!).

I am also getting ERC warnings of gates connected to vdd! or gnd!

Just warnings, don't worry.

... and some latch ups.

?? Sounds dangerous. Latch-up can kill the chip.

 

[nvd]

Oh really!

I will let you know about the exact warning.

I am getting this warning because of interdigitization of transistors in OTA.

I don't want the chip to be dead!

I am not getting warnings for missing connections from the guard ring to vdd! although I got many when gnd! was not connected to METAL1 of the guard ring.

 

[deepak242003]

Oh really!

I will let you know about the exact warning.

I am getting this warning because of interdigitization of transistors in OTA.

you must be getting this error for some particular transistors..... the bulk connection for them is more than maximum recommended by foundry for latchup immunity.... Provide bulk connection for them... surrounding whit respective guarding ( taps ) will make things better......
Let me know if it resolves the issue..


Deepak.

 

[erikl]

Re: unused gate inputs

I am also getting ERC warnings of gates connected to vdd! or gnd!

Just warnings, don't worry.

Thinking twice, I remember some foundries don't allow direct connection of gates to the global power supply rails, because their ESD protection might not be sufficient to protect gate inputs. In this case, 3 different types of connection are recommended:

• extra vdd_ESD & gnd_ESD rails with standard gate protection (series resistor + 2 protection diodes to gnd! & vdd!), or
• the same protection method for every gate input to be connected to gnd! or vdd!, or
• connect every gate input to be connected to gnd! or vdd! to another used input of this gate.

 

[deepak242003]

Re: unused gate inputs

[

• extra vdd_ESD & gnd_ESD rails with standard gate protection (series resistor + 2 protection diodes to gnd! & vdd!)

• 
  
  It sounds similar to CDM protection circuits used to protect the gate of reciver in IO buffers..... I suppose the concept is similar..
  
  Deepak.

 

[nvd]

I have got a reply from the course supervisor:

There is a problem with your submitted layout. You have latchup (LAT3) errors in your design which means that there is not enough substrate contacts close enough to the transistors. There should be one contact within 20 µm of each point inside a transistor (preferably a lot of substrate contacts).

Let's hope, it fixes the problem.

 

[erikl]

Re: LatchUp susceptibility

... There should be one contact within 20 µm of each point inside a transistor (preferably a lot of substrate contacts).

Let's hope, it fixes the problem.

It will, as deepak told you above. Normally, this should already be checked by DRC rules.

 

[nvd]

Connections to vdd! and gnd! can be ignored according to the supervisor.

Can you tell me how can I connect vdd! to guard rings of the capacitors?

I mean which via to use?

And I will add more bulk connections as suggested.

Regards.

 

[erikl]

Re: contact to guardRing

Can you tell me how can I connect vdd! to guard rings of the capacitors?
I mean which via to use?

No via. By contact to metal1 of course!

I am well experienced with layout.

Sorry, I can't believe it!

 

[nvd]

I am getting 1 ring (METAL1) across the capacitor which has been connected to gnd!
Your answer for vdd! connection to the ring is still not clear to me.

Is it either gnd! or vdd! or both connections at the same time to the ring?

The latch-up problem has been fixed as a group member had added too few ND_C and PD_C contacts.

Regards.

 

[deepak242003]

I am getting 1 ring (METAL1) across the capacitor which has been connected to gnd!
Your answer for vdd! connection to the ring is still not clear to me.

You mus b having metal 1 in your guardring instance..You can connect it to vdd! .

Is it either gnd! or vdd! or both connections at the same time to the ring?

vdd for ntap , gnd ! for ptap...

Added after 3 minutes:

Connections to vdd! and gnd! can be ignored according to the supervisor.

I doubt .... without proper biasing guarding will be of no use as they will not collect the carriers ( majority as well as minority ) .Still I am open for any views on this point.


Deepak.

 

[nvd]

Connections to vdd! and gnd! can be ignored according to the supervisor.

These are gates connections and not rings connections.

Regards.