[Cadence - LVS] Problem on Bulks

[supremekai]

Hello guys,

I'm new on Cadence and I'm designing the layout of an OTA and on the LVS I have encountered the following message: "Unmatched Internal Nets" I think regarding the connection between:
->The bulk and the vdd! of the transistors (WHITE on the image)
->The connection between the bulk and the com_diff net (BLUE on the image)

The images of the schematic and layout (regarding LVS) are the following:





How can I join correctly the bulk with vdd! and com_diff nets? Is some contact needed?

Thank you very much in advance!

 

[erikl]

I can't see any bulk taps in your transistor layout. One (nwell) tap in the VDD rail isn't enough - you need bulk taps near all the MOSFETs' sources.