Sam26
Newbie level 2
Hi,
I am doing LINT analysis using cadence HAL. The below mentioned error is generated:
halstruct: *E,CLKDMN Signal from clock domain '%s' is crossing into domain of clock '%s' at flip-flop '%s' without proper synchronization
params HAL {gated_clock_domain_same_as_master="yes"} is set as clock gated output is synchronous to the master clock in our design.
Is there a way to inform the tool about the synchronous relationship between the gated clock outputs?
Please help me with the above mentioned query.
Regards,
Sam
I am doing LINT analysis using cadence HAL. The below mentioned error is generated:
halstruct: *E,CLKDMN Signal from clock domain '%s' is crossing into domain of clock '%s' at flip-flop '%s' without proper synchronization
params HAL {gated_clock_domain_same_as_master="yes"} is set as clock gated output is synchronous to the master clock in our design.
Is there a way to inform the tool about the synchronous relationship between the gated clock outputs?
Please help me with the above mentioned query.
Regards,
Sam