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CADENCE: layout error

lufer17

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Hello everyone, I'm having problems contracting, in CADENCE for some modification that I can't use the layout, I normally did the INVERTER and AND ports, but when I get to the NAND port there are some errors, a message about the library (I'm using the correct library ), it does not look like the components even with the option GENERATE ALL FORM SOURCE and the metals are not in the list. See the image.

NÃO COMP E METAIS.png
 

Dominik Przyborowski

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So do it again, but this time do it properly.
You have clear message, that cdsTechDefLib is currently attached to library NAND.
Reattach library to your tech lib.
 

lufer17

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So do it again, but this time do it properly.
You have clear message, that cdsTechDefLib is currently attached to library NAND.
Reattach library to your tech lib.
sorry i'm not used to software could you explain me step by step how to do this. I'll show a video the first part shows the error NAND even making a new and another drawing inverter. Note: the others I can, but NAND can't.


 

Dominik Przyborowski

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So your statement from post #3 was not true.

If you look on properties of both libraries NAND and INVERTER (by RMB→properties in Lib Manager), you can find a difference in attached technology library. INVERTER is attached to your technology library (in this case tsmc18) while NAND to dummy library called cdsTechDefLib. So, in palette of layout view in one cell you can see a lot of physical layers, while in other only background and text.

During creation of NAND library you have not attached library to your technology.
To fix it do following:
1. close open cells and close data (CIW→File→close data - select all and close)
2. go to (recall from my short memory) CIW→Tools→Technology manager, in tech manager window, choose attach button and point to you design library (NAND) and attach it to tsmc18.
3. Refresh memory: CIW→File→refresh
4. Create new layout view of your cell.
 

lufer17

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So your statement from post #3 was not true.

If you look on properties of both libraries NAND and INVERTER (by RMB→properties in Lib Manager), you can find a difference in attached technology library. INVERTER is attached to your technology library (in this case tsmc18) while NAND to dummy library called cdsTechDefLib. So, in palette of layout view in one cell you can see a lot of physical layers, while in other only background and text.

During creation of NAND library you have not attached library to your technology.
To fix it do following:
1. close open cells and close data (CIW→File→close data - select all and close)
2. go to (recall from my short memory) CIW→Tools→Technology manager, in tech manager window, choose attach button and point to you design library (NAND) and attach it to tsmc18.
3. Refresh memory: CIW→File→refresh
4. Create new layout view of your cell.


Follow the video, it didn't work. Even if you use another new cell in the future, the same error will occur.

 

ranaya

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Follow the video, it didn't work. Even if you use another new cell in the future, the same error will occur.

Can you share a picture of the Library Manager window (Tools -> Library Manager..) by selecting your library in the left half pane ?

like shown below :

Capture.PNG

Also check the permission to that specific library folder.....
 

lufer17

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Thanks to everyone, a friend explained how to resolve and the reason for the error.

Solution: In the library where the folder you are working in (saving the files) must delete all files by calling cdslck.

One of the reasons for the failures: When CANDECE closes in an inspired fashion or executes the shutdown in the wrong way regardless of whether you are running on remote access or on the spot, the cdslck file will appear, according to him, which says that it is a protection measure not to lose the projects.

See the image to facilitate what was said. There are two ways to do this: 1st folder per part to delete cdslck or 2nd go to the search engine and delete all cdslck at once.

Note: You must exclude all files by calling cdslck (with their derivations).

CDSLCK.png
 

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