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Cadence Layout cannot show PDK graph

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ovicovic

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1. Configuration: Cadence IC617 + MMSIM151 + Calibre 2015.
2. PDK: TSMC CRN65GP, install using pdkInstall.pl in PDK.
3. I am studying the LNA tutorial given by TSMC docs. The schematic simulation is fine. But in the layout, the Instance in the PDK library is not displayed, just a transparent box, after press "shift + F", the box like this "☒". If I add Instance in my Library, an error will pop up.
CDF: An error occurred when evaluating callback.
Callback: m->display => iPDK_isSchematic()
Message: *Error* eval: undefined function - iPDK_isSchematic
CDF: An error occurred when evaluating callback.
Callback: mismatch->display => iPDK_isSchematic()
Message: *Error* eval: undefined function - iPDK_isSchematic
1654742617369.png

4. Open the layout of Cell nmos_rf in the PDK Library, there is a warning prompt, but the layout is displayed normally, with colors and layers.
In Layout *WARNING* (DB-220704): The Pcell super master: TSMC_CRN65GP/nmos_rf/layout is not s SKILL super master. The usage of non-SKILL Pcells in virtuoso is not a supported feature.
1654742703429.png
 

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