Thank you for the clarification. I believe my issue it that I have too many I/O pins for the area needed to fit the standard cells. When the IO pin placement happens based on minimizing routing, this results in congestion in certain areas. If the logical IO pins were spread out more evenly, this congestion would not have corrected, but this might be at the expense of more area needed for the routing.
I am looking for options that I can force the IO pin placement to be spread out. I tried the editPin option after the initial placeDesign, which lets you spread on an edge, but it was not successful. If you have other options that you could suggestion that would help reduce io congestion, at the expense of area, please let me know.
My initial study is focused on the impact of area of blocks, so I'm not worried about the precise placement for IO pins.
Thanks again for all of your help!!