cadance error in designing the layout of Flipped Voltage Follower

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neeraj yadav

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I am using Cadence for the designing an flipped voltage follower.
I'm a bit stuck understanding what these error messages mean in the DRC checker.
if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:

1. Welnotr_StampErrorFloat
(NWEL is highlighted)

2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted

3. 4:17N Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted
please reply me...
please...



thanks
 

Perhaps N+/P+ implant layers overlaped.
 

You need P+ substrate taps ("pick ups") closer than 20µm to every well.
 


it looks like you do not have body ties in your layout, you need n+ to high voltage (higher than or equal to any PFET source terminals in that well) in Nwells and p+ to low voltage (lower than or equal to the source of all NFETs in that well) in Pwells

If this is an analog layout you should have a body tie close to all FETs
 

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