Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
to my exp... you require more functions which export the verilog/vhdl signals to C and for debugging in the ref model becomes night mare... I agree that speed matters a lot but need to take care for the memory leaks in that!!
If soc is bigger then i suggest to go for system-c based verification strategy
otherwise go for system Verilog based verification
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.