Bypass for 'for' loops ??

[Resistance]

hi friends,


Give me a formula to bypass for loops in my design..
any general formula exist to avoid synthesis demons like for and while..

Clear explanantions with links are most welcome..

Regards

 

[eda_wiz]

think hardware and rewrite your code to remove loops...
see one example here
https://www.asic-world.com/examples/verilog/decoder.html#Decoders

 

[snake_eyes]

What do you exactly mean by "Bypassing" the for loops?

 

[verilog_coder]

for loops are usually used in initialization or for some ram/rom models for simulation purposes. There is no special method to bypass for loops. You need to know what the purpose of for loop is in your code and then write other code to replace that for loop.