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Building a XOR Gate for minimizing EDP

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Apr 5, 2010
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I'm looking to build a 3input XOR gate that minimizes EDP.

I've been looking through web and found some some enticing designs:


from wikipedia

**broken link removed**
**broken link removed**

They all use 12 transistors so it is hard to tell which one is the "best".
I'm using the XOR for a full adder which is to be implemented into a 32 bit ALU.

I was wondering which one of these is the "best" ?

In my digital design class, we've always talking about nands, nors, and inverters.
An AND Gate can be made using a NAND and Inverter but this seems like a extraneous use of transistors.
Is there another way of making an AND gate? Similarly OR?

In case it's useful the website below has a couple of 2-input XOR gates which are remarkable for having a low parts count.

One uses a single transistor.

There may be a way to convert one or the other for 3-input use.

4QD-TEC: Discrete logic circuits

Scroll down halfway. ('EXOR gates')
I am not expert at this design level since designing ICs likely follows more rules than designing ordinary circuits, in order to let the integration be practical as specifications and economical for production.

So I think, a professional CAD program for ICs (say digital) gives the designer the end specifications (of the inputs, outputs... etc) and the estimated cost of production of what he is designing. This helps him do some tradeoffs.

While Fang and Cheng circuits have the same number of transistors (PMOS and NMOS), they surely differ in some characteristics. For example I won't be surprised if they have different propagation delays for some (if not all) possible transitions. So choosing which one is better depends on the other parts of the IC.

About NAND vs AND and NOR vs OR, I think, though I may be wrong, that naturally building NAND or NOR with the active elements used in the ICs seems to be easier than directly making AND or OR. But you can always check to how far this could be true.


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