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The clock buffers are designed with some special property like high drive strength and less delay. Because clock net is the more fanout and longest running net. Even you can use the normal buffers in the clock path.
Normal buffers are designed with p/n ratio such that sum of rise delay and fall delay is minimum (atleast for high speed libraries) whereas Clock buffers have equal rise and fall slew rates. Reason for doing this is to prevent duty cycle of clock signal from changing when it passes through a chain of clock buffers.