Buffering FPGA IO pins

[shaiko]

Many times I see buffer ICs used on the IOs of an FPGA.
Most commonly, they are used on those pins that lead to an external connector from the PCB.
As far as I understand, this is done to protect the FPGA... I.E - if something burns out it'll be the buffer IC (that's easier and chipper to replace) and not the FPGA.

What do you think about this design practice ?
Is it really worthwhile ?

 

[RCinFLA]

Depending on the process node (transistor geometry size) on FPGA the I/O's may not tolerated the voltage levels needed by the external circuit (like driving 5v logic from an I/O having a 3.3v max rating). Another reason could be drive current needed to drive the loads on the I/O's of the FPGA.

As you mentioned, there is the cost of an FPGA and desire to add some extra isolation protection, just in case.

 

[completelyuseless]

yes, as the previous poster said, some of the time its possible to control the voltage level needed for the interface only through a buffer or phy chip. but its not always the best route. if the pins are bi-directional, control on these buffers may become difficult.

an interesting example is an Ethernet interface. you can use a phy chip that controls the voltage levels that are needed to drive the halo connector. you don't need to though. you can wrap this in a RIO core. but you waste a GTX on gigabit ethernet. the RIO core will handle the voltage levels needed, but would you want to waste a GTX tile on gigabit ethernet?

it also depends on the maturity of the FPGA technology. in the past people would use deserializer/serializer chips, and connect the parallel data to the FPGA. these chips contained the buffers needed to drive the device, eg ADC or DAC. now its easier to do that in an FPGA with serdes/oserdes primatives.

so no generic answer, it all depends on what you are doing.

hope that helps.