Buck Power Supply PCB Design Layout Help

[Rocketman46]

Hi All,

I need a bit of circuit layout guru advise. I have currently made a 2 layer buck SMPS board. Although it functions, to much noise is on the board. This board was designed with signal and power on the top layer, and a Gnd plain on the bottom layer.

My next step is to build a 4 layer PCB to try to reduce the noise, but I am little unsure how to arrange the layers. I was thinking the below arrangement:

* Top layer - Componets and Power tracks.
* Second layer - Gnd plain.
* Third layer - signal wires, gate drives, voltage feedback etc.
* Fourth layer - Gnd plain.

Thanks again.

Rocketman46.

 

[D.A.(Tony)Stewart]

The copper layers can be used as a low ESR capacitor with dielectric or a patch antenna with inductive feedthru's depending on many other variables not included in your assumptions.

Firstly specify exactly noise levels you measured and what you expect?

Is it just conducted noise on regulated output? What about input noise, radiated noise etc.

Examine the ESR and ESL on your storage capacitors compared to load resistance and look for opportunities to compensate or improve these first.

 

[andre_luis]

Although each arrangement result in different performance feature ( rework ability, shielding, etc.. ), most guidelines recommends arrangements as bellow:

• Top layer - Components / SIGNAL
• Inner top layer - POWER
• Inner bottom layer - GND
• Bottom layer - SIGNAL

 

[nikhilmahasvar]

Have you routed power ground and signal ground seperately ? The placement of input filter cap also plays a major role...
I think double side will be quiet sufficient unles you are very particular about the PCB size.

 

[Rocketman46]

Hi all,

Thanks for your input.

The board suffers from inductor jitter, this was the reason for going for 4 layer to reduce the noise. Both grounds are seperate and are join under the ic using a star point.

And yes the board is small and possibly some cross talk is taking place.

Any other ideas are welcome.

thanks.

 

[marce]

Have you a schematic, a view of the board and the controller IC. SMPS layout is critical, especially minimising the loop area of the input and output loops where there is a hi dI/Dt.