Hi,
AFAIU, yes, it is. LC output filters suck, IMO - they lower response time options a lot.
It can't be higher unless you want a 'lovely' bump in the response at the resonant frequency.
If you think about it, for a stable output voltage we are very unlikely to need e.g. fSW of 300kHz and a control loop that checks for errors and corrects for errors 300,000 times a second...
Or in my mind - maybe this is wrong - an op amp (which will always have a limited bandwidth) that is correcting and turning off and on thousands of times a second may eventually swing out of control and begin to oscillate. Happy for corrections if these comments are inaccurate.
The general idea can be reduced to laconic "roll the gain off early". The EA gain has to be less than 1 for it to be stable, so you deal with that as early as possible, it's not exactly related to fSW, more to the poles and zeroes, and especially to the right-half-plane zeroes in DC-DC like Boost and SEPIC but not Buck converters.
p.3 of 'Buck Converter Stable Compensation Networks', p.3 of 'Closing the Feedback Loop', p.30 - p-31 of 'Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier' paragraph: "There are two reasons to design for lower loop bandwidth. First, due to relatively large value of the selected output capacitors, usually there is no need to design for a high loop bandwidth to achieve satisfactory transient response. Second, when the resonance frequency of the regulator is much lower than the designed loop bandwidth, a relatively high gain-bandwidth is demanded from the error amplifier. Therefore, to avoid running into the gain-bandwidth-product limitation of the error amplifier, it is recommended to design for a lower loop bandwidth."
My advice may be bad, but the RAR folder is full of goodies!