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[SOLVED] Buck Converter Feedback Loop - Stability Criteria

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FreshmanNewbie

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Question 1 :

I am having some trouble understanding the Stability criteria of the Buck Converter Loop Stability which says, "The cross over frequency should be less than 1/8th or 1/10th of the switching frequency ".

Can someone tell me with the switching frequency pulse waveform and the cross over frequency waveform - on why the cross over frequency should be less than 1/8th or 1/10th of the switching frequency.

I think it would be clear if someone shows me the waveforms of the switching frequency and the crossover frequency and explain with the above criteria.
 

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Hi,


In a SEPIC it's related to RHPZ, in a buck, not sure why the habitual 1/8th to 1/10th fSW. It's presumably related to the location/placement of poles and zeroes.

I remember that stability is linked to and gain margins at fC and when phase reaches -180°, something like that. TND352 pdf explains it better.

In attached slva301 pdf, page 13 onwards covers this topic, afaiu, "One possible algorithm for placing the poles and zeros is demonstrated by an example. Besides deciding where to place the poles and zeros, the compensator gain also determines the crossover frequency of the loop. The crossover frequency selection is based on the switching frequency and the desired loop transient response."
 

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  • slva301.pdf
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  • TND352-D-1.PDF
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d123

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Hi,


Got my notes again. If you haven't read them yet, among many that explain it well are "Control of Switch Mode Power Supplies - Refresher on Stability Analysis" and slup340, "Switch-Mode Power Converter Compensation Made Easy"

Need to reduce gain to < 1 before ~ fSW/10, prevent control loop from 'seeing' switching action.

For stability: phase < 180°, > 45° when gain passes through 0, and gain < 0dB when phase passes through 180°.
If gain rises again = metastable/unstable (above frequency where it occurs, I think).
 

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The combination of inductor and capacitor can create unwanted resonant behavior. To avoid wild voltage swings and ringing, therefore the resonant frequency needs to be very different from the switching frequency.
 

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The combination of inductor and capacitor can create unwanted resonant behavior. To avoid wild voltage swings and ringing, therefore the resonant frequency needs to be very different from the switching frequency.
Thank you for the comment. So, are you saying that the resonant frequency of the Output Inductor and Capacitor of a buck converter is the cross over frequency of the control loop?

And if so, why should the resonant frequency of the LC be less than the switching frequency of the converter? Why can't it be higher than the switching frequency?
 

KlausST

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Hi,

"Switching" means there are overtones. The switching signal contains frequencies higher than the switching frequency itself.
In either case it would cause resonant oscillations. This is not what one wants. Usually one wants DC. But DC is the lowest (im-) possible frequency.
You don't want ringing, you don't want oscillations, you don't want frequency.
Only a low resonant frequency filter can achieve this.

Klaus
 

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Hi,

AFAIU, yes, it is. LC output filters suck, IMO - they lower response time options a lot.

It can't be higher unless you want a 'lovely' bump in the response at the resonant frequency.

If you think about it, for a stable output voltage we are very unlikely to need e.g. fSW of 300kHz and a control loop that checks for errors and corrects for errors 300,000 times a second...

Or in my mind - maybe this is wrong - an op amp (which will always have a limited bandwidth) that is correcting and turning off and on thousands of times a second may eventually swing out of control and begin to oscillate. Happy for corrections if these comments are inaccurate.

The general idea can be reduced to laconic "roll the gain off early". The EA gain has to be less than 1 for it to be stable, so you deal with that as early as possible, it's not exactly related to fSW, more to the poles and zeroes, and especially to the right-half-plane zeroes in DC-DC like Boost and SEPIC but not Buck converters.

p.3 of 'Buck Converter Stable Compensation Networks', p.3 of 'Closing the Feedback Loop', p.30 - p-31 of 'Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier' paragraph: "There are two reasons to design for lower loop bandwidth. First, due to relatively large value of the selected output capacitors, usually there is no need to design for a high loop bandwidth to achieve satisfactory transient response. Second, when the resonance frequency of the regulator is much lower than the designed loop bandwidth, a relatively high gain-bandwidth is demanded from the error amplifier. Therefore, to avoid running into the gain-bandwidth-product limitation of the error amplifier, it is recommended to design for a lower loop bandwidth."

My advice may be bad, but the RAR folder is full of goodies!
 

Attachments

  • Buck Converter Stable Compensation Networks Intersil tb417.pdf
    206.1 KB · Views: 62
  • Closing the Feedback Loop TI slup068.pdf
    647.8 KB · Views: 61
  • Compensator Design for Buck with VM EA an-1162.pdf
    1.3 MB · Views: 90
  • Compensation and Control.rar
    36.3 MB · Views: 57

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Hi,

"Switching" means there are overtones. The switching signal contains frequencies higher than the switching frequency itself.
In either case it would cause resonant oscillations. This is not what one wants. Usually one wants DC. But DC is the lowest (im-) possible frequency.
You don't want ringing, you don't want oscillations, you don't want frequency.
Only a low resonant frequency filter can achieve this.

Klaus
Thank you for the answer. So, the cross over frequency means the resonant frequency of the output LC Filter, am I correct?

And our switching frequency needs to be higher by 1/8th or 1/10th than the resonant frequency of the output LC Filter, to avoid the LC higher harmonic frequency affecting the internal switching frequency of the buck converter?

Is my understanding correct?
 

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And our switching frequency needs to be higher by 1/8th or 1/10th than the resonant frequency of the output LC Filter, to avoid the LC higher harmonic frequency affecting the internal switching frequency of the buck converter?
No, not higher by 1/8 or 1/10 but higher by a factor of 8 or 10.

And read through some basics of LC filters.

Klaus
 

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No, not higher by 1/8 or 1/10 but higher by a factor of 8 or 10.

And read through some basics of LC filters.

Klaus
Thank you. But, the cross over frequency means the resonant frequency of the output LC Filter, am I correct?

And my reasoning with the avoiding of the LC higher harmonic frequency affecting the internal switching frequency of the buck converter , is also correct right?
 

d123

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Hi,

You seem to be mixing up concepts, I did when I started looking into this stuff.

Switching frequency is from 5 to 10 times, or 8 to 10 times, depending on what design note you read, higher than the crossover frequency of the control loop. Crossover is the frequency when the op amp runs out of gain, besides phase margin. They are different things. The control loop is checking whether Vout is at the correct level. Switching frequency is set a lot higher and is duty cycle dependent. The control loop is an op amp - it has finite bandwidth, the switch is a transistor whose bandwidth is more than likely several orders of magnitude higher than the op amps, compare your selected error amplifier's GBW in the graphs in the datasheet to the MOSFET's ft value in its datasheet.

An output LC filter tends to lower the crossover frequency as it's hard to select components that have a high resonant frequency and that filter unwanted noise from the output at the same time (electronics: you can't have your cake and eat it, it's usually about accepting unhappy mid-points between the desirable and the implementable), so it's advisable to calculate the LC output filter before bothering to calculate component values for your control loop to avoid doing the iterative compensation calculations twice.

Example, just a made-up example to clarify what you should be aiming for:
fSW = 100kHz
LC output filter = 1kHz
Therefore:
make the control loop fC = 500Hz

Attached are several application notes about LC second-stage output filters and LC input filters, you'd have to sift through them to find what's of interest to you right now, it's all pertinent and reputable information.

Do the LC output filter calculations first before calculating the control loop compensation, trust me. It's euphemised as 'cumbersome and iterative', and doing 'cumbersome and iterative' calculations twice is time wasted. I may seem a fool but I actually do know a couple of useful things.
 

Attachments

  • Output Noise Filtering for DCDC Power Modules snva871.pdf
    372.7 KB · Views: 42
  • Power Tip #1_ Picking the right operating frequency for your power supply _ EE Times.pdf
    180.2 KB · Views: 46
  • Power Tip #2_ Taming a noisy power supply _ EE Times.pdf
    365.6 KB · Views: 41
  • Power Tip #3_ Damping the input filter — Part 1 _ EE Times.pdf
    181.9 KB · Views: 47
  • Power Tip #4_ Damping an Input Filter ” Part 2 of 2 _ EE Times.pdf
    161.2 KB · Views: 70
  • Power Tip #4_Damping an Input Filter Part 2 of 2 _ EE Times figure-3.jpg
    Power Tip #4_Damping an Input Filter Part 2 of 2 _ EE Times figure-3.jpg
    34 KB · Views: 67
  • Power Tip 54_ Use 2-section filter for low-noise power supply _ EE Times.pdf
    176.8 KB · Views: 48
  • Simple Solution for Input Filter Stability Issue in DCDC Converters slua929a.pdf
    1.5 MB · Views: 51
  • SMPS filters 1 second stage filter design.pdf
    84.6 KB · Views: 50
  • SMPS Output Filtering Limitations.pdf
    93 KB · Views: 42
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