Has the 2 blocks PNR completed? If yes, Has the ETM models generated by the PT/sign off tool? If done, then most of the information is available at the .lib's of your blocks and write out correct SDC at the top level by giving correct number for set_input_delay and so..
This would generated faster optimizations at the top level,
if any of the above has not completed, then yes u can use both the sdc's and make sure to have correct clock definations and synthesis at the top level, Don't forget to group it at top.