Jul 9, 2009 #1 G grubby23 Junior Member level 3 Joined Nov 22, 2007 Messages 30 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,606 Hi I am having a design with more than 15 modules. I wonder if in Xilinx ISE 10 there is a possibility to see the contribution of those modules to the overall number of slices. Would make things easier than synthesis each module itself. Thanks
Hi I am having a design with more than 15 modules. I wonder if in Xilinx ISE 10 there is a possibility to see the contribution of those modules to the overall number of slices. Would make things easier than synthesis each module itself. Thanks
Jul 13, 2009 #2 O OutputLogic Junior Member level 2 Joined Jun 11, 2009 Messages 23 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Location San Jose, CA Activity points 1,370 If you use Virtex 5, MAP report will contain "Section 14 - Utilization by Hierarchy" with utilization of different modules in your design. Hope that helps. OutputLogic
If you use Virtex 5, MAP report will contain "Section 14 - Utilization by Hierarchy" with utilization of different modules in your design. Hope that helps. OutputLogic