Breakdown of module utilisation

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grubby23

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Hi

I am having a design with more than 15 modules. I wonder if in Xilinx ISE 10 there is a possibility to see the contribution of those modules to the overall number of slices.
Would make things easier than synthesis each module itself.

Thanks
 

If you use Virtex 5, MAP report will contain "Section 14 - Utilization by Hierarchy" with utilization of different modules in your design.

Hope that helps.
OutputLogic
 

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