boundary scan (JTAG) does not find xilinx FPGA

[schouten_tjeerd]

I can't get the boundary scan to detect my devices. I have a homemade board with a Xilinx Spartan 3E (xc3s100e) and a Xilinx PROM attached (XCF01SVOG20). The JTAG device I use is a Digilent XUP USB-JTAG Programming Cable. The scan only finds one device instead of two and it is is labeled "unknown". A popup is displayd: "Unknown device query - Do you have a BSDL or BIT file for this device?".

Here is the output:

// *** BATCH CMD : setCable -port usb21 -baud 750000
Connecting to cable (Usb Port - USB21).
Checking cable driver.
Driver file xusb_emb.sys found.
Driver version: src=1029, dest=1029.
Driver windrvr6.sys version = 8.1.1.0. WinDriver v8.11 Jungo (c) 1997 - 2006 Build Date: Oct 16 2006 X86 32bit SYS 12:35:07, version = 811.
Cable PID = 0008.
Max current requested during enumeration is 74 mA.
Type = 0x0004.
Cable Type = 3, Revision = 0.
Setting cable speed to 750 KHz.
Cable connection established.
Firmware version = 1302.
File version of D:/Xilinx/10.1/ISE/data/xusb_xlp.hex = 1302.
Firmware hex file version = 1302.
Type = 0x0004.
ESN option: 00000000000000.
PLD file version = 0012h.
PLD version = 0012h.
Type = 0x0004.
ESN option: 00000000000000.
Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify
PROGRESS_START - Starting Operation.
Identifying chain contents ....INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part.
'1': : Manufacturer's ID =Unknown , Version : 14
INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time = 0 sec.
// *** BATCH CMD : identifyMPM


///////////////////


Any ideas?

 

[laserbeak43]

i had problems with ISE 11.1 Webpack, if that's what you're using, and had to downgrade, in order for my spartan 3e starter kit to be fully recognized. I have no idea what your problem is, but maybe that will help.
good luck.

 

[schouten_tjeerd]

I have WebPack 10.1 What version did you downgrade to?

 

[farhada]

I had a lot of problems with the JTAG on my laptop with ISE 10.1 the olny way I could fix it was to have a clean windows installation and then installed ISE and a fez other programs as the only applications.

The problem is the USB driver that is not working properly and I have no idea why is that.

 

[schouten_tjeerd]

It works now. The GND and VCC pins of the PROM chip where not correctly soldered. But I have a new problem now. The code runs fine if it is programmed directly to the FPGA but if it is start up in master serial mode via the PROM, it doesn't work. DONE never goes high and the CCLK keeps clocking.

Any thoughts?

Added after 1 hours 32 minutes:

I fixed the PROM bootup as well. The problem was the CCLK signal quality. I changed from serial termination (as used in the digilent designs) to a parallel termination as per Xilinx document UG332 (Xilinx UG332 Spartan-3 Generation Configuration User Guide) Figure 2-3

 

[decibel08]

sorry to revive an antiquated thread, but i have a similar situation to the OP.

i'm using a spartan 3E series FPGA (XC3S250E-4TQG144C) with the recommended xilinx prom XCF02SVOG20C. when i connect with the iMpact tool, the boundary scan does not find either device. i get this error: "ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage."

i've recently used this same programming device (xilinx usb II) successfully on an older CPLD (X9572 series), so i am relatively certain the cable part of the chain is ok. i believe i followed the datasheet connections to the T, and the soldering looks good. the connections are as follows:

jtag TDI -- fpga TDI (pullup)
jtag TMS -- fpga TMS and prom TMS (pullup)
jtag TCK -- fpga TCK and prom TCK
jtag TDO -- prom TDO
fpga TDO -- prom TDI
fpga DONE -- prom \CE
fpga PROG_B -- prom \CF
fpga INIT_B -- prom \OE/reset
prom DO -- fpga DIN
fpga CCLK -- prom CLK

mode select bits M2:0 are set for master serial. CCLK does run on its own when the board is powered up and the signal quality is very clean. all power supplies are stable (3.3, 2.5, 1.2).

any ideas?