Bootstrapped switch Sample and Hold circuit - with dummy and without dummy

Dear all,

I am designing a low-to-medium S/H circuit for an ADC. The sampling switch is a bootstrapped switch to linearize the on-resistance.

I first designed a bootstrapped switch, and I simulated the waveforms and obtained DFT and THD in cadence with the calculator.

After that, I also designed a dummy switch to cancel the charge-injection and clock feedthrough. I think the results is not bad.

I also obtained the new output DFT and THD. However, I found the DFT plot of the S/H output with and without dummy is almost the same. ( the 2nd harmonic, 3rd harmonic, magnituedes are almost the same)

But from the transient simulation results I can see the S/H with dummy actually has betteer accuracy.

Can anyone command on this?



You can see the three lines for Vin, Vout_no_dummy and Vout_withdummy, respectively.

I also attached the two DFT plot here.

It can be seen that the 2nd harmonic distortion for S/H with dummy is actually 1dB worse than without dummy.

Is it possbile that the DFT plot is not correct?

I did DFT with coherent sampling. Please take a look

In a first order, charge injection causes a fixed (or linearly voltage dependant) offset but only few non-linearity. Thus it doesn't show up in DFT. Adding the compensation FET can even add some non-linearity, as your measurement shows. Not surprizing in my opinion.

FvM said:

In a first order, charge injection causes a fixed (or linearly voltage dependant) offset but only few non-linearity. Thus it doesn't show up in DFT. Adding the compensation FET can even add some non-linearity, as your measurement shows. Not surprizing in my opinion.

Click to expand...

Thanks a lot man. I understand now.

That really helps.