Still you need Vg above one of the terminals by some volts. The lower of S, D in this case looks like D, at ~+4V.
Not sure how the CL node (D) ever got to 4V but it sure seems uninterested in going higher.
Maybe set up simpler, with just the switch FET, its +15V and CL, and drive the gate with a 0-5V pulse source that has its return (-) tied to CL rather than gnd! Then you can see what the FET switch does when fully (-ish) driven. It may be that the on resistance of the smallish (21/0.6) FET is too high to meaningfully move the 250pF capacitance (at least, with low gate drive). I know that there would be a lot more width than that, for a digital output buffer expecting a smaller load, generally.
21/0.6 means you're using a 5V device but you have a 15V supply, no?