entity BOOL isgeneric(
BOOL1 :boolean:= false;
BOOL2 :boolean:= true
);endentity;architecture behave of BOOL isbeginprocessbeginif(BOOL1 = false)thenreport"BOOL1 is false";elsereport"BOOL1 is true";endif;if(BOOL2 = true)thenreport"BOOL2 is true";elsereport"BOOL2 is false";endif;waitfor 100ns;endprocess;endarchitecture;
You'll note that you use 1 for true and 0 for false, I believe anything other than 0 (within reason or 32-bits!) will be considered a true in VHDL when passed from Verilog. You could always use a verilog define for the true and false.
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
// using a define`define true 1`define false 0
.BOOL1 (`true),
.BOOL2 (`false)// or using a localparam/parameterlocalparam true =1;localparam false =0;
.BOOL1 (true),
.BOOL2 (false)