If I may suggest... an idea..
Books are all very explicatives, but it is often very easy to assume that you did understand a portion of a langage and if the assumption is incorrect you may end up in disaster.. Specifically in VHDL. An alternative to books, is an interactive tutorial such as the ones provided by ESPERAN which let you check as you learn if you really understood what you just learn.
I believe they have two different levels for both Verilog and VHDL.
And of course the ultimate, to triple check that what you had in mind will be implemented in the silicon is to use modelsim to verify that your logic is really working, and leonardo spectrum to have a schematic view of how your idea has been implemented. Some will say that it is an expensive way.. But.. :lol:
Happy new year all..
Have fun..