Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I had learnt programming FPGA from Kevin Skahill's "VHDL for Programmable Logic" and VHDL from"Peter Ashenden's "The Designer's Guide to VHDL 2nd Edition". For Verilog - Brown's "Fundamentals of Digital Logic with Verilog Design". I think that this books are very good and useful for beginers. Also "Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition" should be helpful.
Next you should read documentation for implementation and synthesis software(which support yours FPGA), where you can find inforamation which construction of HDL are supported and which aren't and howto write optimal code.
And also application notes where you can find how to use embedded blocks of FPGA.
I have learned VHDL, and started with McGraw.Hill.VHDL.Programming.by.Example,
I think this book is very good for beginner.
Now there is a ebook of it available at:
**broken link removed**
Books are all very explicatives, but it is often very easy to assume that you did understand a portion of a langage and if the assumption is incorrect you may end up in disaster.. Specifically in VHDL. An alternative to books, is an interactive tutorial such as the ones provided by ESPERAN which let you check as you learn if you really understood what you just learn.
I believe they have two different levels for both Verilog and VHDL.
And of course the ultimate, to triple check that what you had in mind will be implemented in the silicon is to use modelsim to verify that your logic is really working, and leonardo spectrum to have a schematic view of how your idea has been implemented. Some will say that it is an expensive way.. But.. :lol:
Some EDA tools has the ability to exchange the code of VHDL to\from Verilog. the main purpose of such code to simplify the design, not to learn many language for coding and forget the main function of it.
I don't think that there is an actual difference between VHDL and Verilog they are just 2 different languages but they finally do the same thing as good as both do it. Your personal opinion will finally chose.