block memory access prob (ISE & Quartus)

[childs]

Recently while I am programming a Spartan-3E board using ISE10.1 web edition, I came across the problem where my design passed the compilation and synthesis where i set the timing constraint at 20ns (50MHz as i am using the onboard oscillator). No warning or error is shown but the memory write operation is not performed. However after program to Spartan-3E, the memory write operations sometimes cannot be performed. Note that is "sometimes" cannot be performed, and it is very unsteady.

I came across the same problem while I was using Quartus2 web edition months ago. No warning or error is shown but the memory write operation is not performed. It was solved as I put the timing constraint to 10ns, and run the simulation later using clk speed of 20ns period. However in the Spartan-3E design now, I cannot afford to put timing constraint of 10ns as the logic is not sufficient.

Does anybody know about/encounter this problem? Any idea how to solve?? Thanks in advance...

 

[sheik_vb]

Hi,

Can you post your rtl...

 

[FvM]

block memory access prob (ISE & qu(at)rtus)

50 MHz is rather slow for on chip memory, I expect a basic design problem.

 

[childs]

Re: block memory access prob (ISE & qu(at)rtus)

50 MHz is rather slow for on chip memory, I expect a basic design problem.

The bugs on Spartan-3E board appears to be other problem. However this bug does happen few months ago when i was designing in Quartus 2.

...I came across the same problem while I was using Quartus2 web edition months ago. No warning or error is shown but the memory write operation is not performed. It was solved as I put the timing constraint to 10ns, and run the simulation later using clk speed of 20ns period....

 

[mmarco76]

block memory access prob (ISE & qu(at)rtus)

Have you set all the constraint?
Not only the clock one but also setup and hold?
If yes maybe you've to correct some of that for traces to be taken in account.
Take your digital scope and look at your signal at the Memory side (when you write) and then do the same at FPGA side (when you read) in order to set up the right constraints.

Added after 4 minutes:

Ops, maybe I'we read wrong..
You're not speaking of an external RAM but of an internal one, right? (in previous thread I've suggested what to do if it were outside of FPGA)
If it's of the internal one, on quartus you've to put attention on all the option you can choose and be sure that all your write and read code is synchronous with the Memory.
I mean that if the memory is 50MHz, all your signal MUST be generate with THE SAME 50 MHz.
If you don't do it (but maybe you generate some signal in different way) you NEED to set all the timing constraint because Quartus will analyze it right (I mean multicycle if you generate signal with different but related clock or set up and hold for different way signal generation).
Usually that's a pain so I suggest to do a fully synchronous design, that is always better.