Blind via vs regular via

[m.charge]

I need help to decide between designing a PCB with or without blind via's.

Currently, I'm working on the 6 layers PCB, thickness 0.062", the main component that required blind via is LGA173 package with 13.7 mil pads pitch.

I have the option to proceed without the need for blind via's (by routing some of the signals through regular full stack via'a that can be placed between the chipset pads), I tried to ask the board house which option they recommend for better manufacturability and durability but I didn't get a clear answer, I hope I can get some advice to help me make my decision.

I really appreciate any help you can provide.

 

[FvM]

Really 0.35 mm pitch? I know RS9116N-CC0 in LGA173, but it has 0.7 mm (27.56 mils) pitch. Very effective for BGA/LGA is VIPPO (via in pad plated over) technology, less expensive than blind/buried vias. If you have difficulties to achieve wiring on 6 layers, adding layers is probably cheaper.

But optimal technology depends on circuit type, above considerations must not necessarily apply to your design.

 

[tepalia02]

Blind vias can help reduce signal interference.They can enhance thermal dissipation. It's important for components with high power dissipation like LGA packages.

 

[D.A.(Tony)Stewart]

If you specify micro-vias or laser cut vias, then compute the via capacitance, inductance and SRF from any S/W tool and add the path length delay-lines to determine the distortion or loss added and compare TH via with blind via.

But also consider via max. current for a 20'C temp rise and adding more vias if necessary.

Generally in high-volume the cost is driven by total layer * copper area whereas in prototypes it is not.

 

[barry]

Blind vias can help reduce signal interference.They can enhance thermal dissipation. It's important for components with high power dissipation like LGA packages.

I'm not sure how blind vias, as opposed to through vias, can enhance thermal dissipation. You're going to be able to dissipate heat with copper on an outer layer a lot better than an inner layer.

 

[m.charge]

Really 0.35 mm pitch? I know RS9116N-CC0 in LGA173, but it has 0.7 mm (27.56 mils) pitch. Very effective for BGA/LGA is VIPPO (via in pad plated over) technology, less expensive than blind/buried vias. If you have difficulties to achieve wiring on 6 layers, adding layers is probably cheaper.

But optimal technology depends on circuit type, above considerations must not necessarily apply to your design.

Sorry, I meant the spacing between the pad edges is 0.35 mm, the pitch is 0.70 mm

I was thinking about VIPPO and it's doable on my PCB but I need to confirm with the board house, have you tried that with the 0.35 mm pad size? if so, can you provide some more information like the size of the hole, etc?

Thanks

--- Updated Oct 16, 2023 ---

Blind vias can help reduce signal interference.They can enhance thermal dissipation. It's important for components with high power dissipation like LGA packages.

Are you referring to the signal interference on the outer layer?

--- Updated Oct 16, 2023 ---

If you specify micro-vias or laser cut vias, then compute the via capacitance, inductance and SRF from any S/W tool and add the path length delay-lines to determine the distortion or loss added and compare TH via with blind via.

But also consider via max. current for a 20'C temp rise and adding more vias if necessary.

Generally in high-volume the cost is driven by total layer * copper area whereas in prototypes it is not.

View attachment 185466
View attachment 185467

Are you aware of any free tool that can do this job?

Also, talking about current flow, I have the option of using 8 mil hole size for the blind via which is good for signals but I have a bit of concern about the current flow.

 

[D.A.(Tony)Stewart]

Saturn's tool is free.

 

[FvM]

I was thinking about VIPPO and it's doable on my PCB but I need to confirm with the board house, have you tried that with the 0.35 mm pad size? if so, can you provide some more information like the size of the hole, etc?

I haven't yet implemented 0.35 mm size VIPPO. You should check with the PCB house. If pad size is a problem, you can also consider solder mask defined pad.

 

[m.charge]

I haven't yet implemented 0.35 mm size VIPPO. You should check with the PCB house. If pad size is a problem, you can also consider solder mask defined pad.

I already sent them an email to ensure the pad size is okay, but I haven't gotten a response yet.

I also validated the dog-bone design strategy, it seems okay with 5 mil clearance, I can insert a 15 mil via in between the pads with 8 mil drill hole, thoughts?

 

[FvM]

This standard escape route design should definitely work.

 

[m.charge]

This standard escape route design should definitely work.

Thank you!

Appreciate your help.