biju4u90
Full Member level 3
I want to enable Reverse Loopback Mode (pre - CDR) in Arria 10 Transceiver PHY. In the User guide of the same, it is seen that I should perform a read-modify-write to address 0x2E1 to set bit 0 to 1’b1 for "serial loopback mode". But in the excel sheet for register map, it is given that 0x2E1 enables the rx_seriallopbken feature in the transceiver. Setting 1’b1 enables reverse serial loopback. So, should I set 0x2E1 to 1'b1 for reverse serial loopback mode??
Again, in the Transceiver PHY user guide, it is said to set 0x13C[7], 0x11D[0], 0x132[5:4], 0x137[7], 0x142[4] for reverse serial loopback mode. But I don't see any explanation what changes these bit settings do
Again, in the Transceiver PHY user guide, it is said to set 0x13C[7], 0x11D[0], 0x132[5:4], 0x137[7], 0x142[4] for reverse serial loopback mode. But I don't see any explanation what changes these bit settings do