binding the 3 port in single segment

[sdmcet]

hi,i want to bind the following code in single segments.the following code consist of 3 libraries and 3 ports,so my problem is make it as single port,so that it's very easy for me to create test bench.please help me.
thank u

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Code VHDL - [expand]
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library ieee; --LIBRARY DECLARATION
use ieee.std_logic_1164.all;
 
entity gencoder24 is  --ENTITY DECLARATION
 port(  start:in std_logic;
    insym:std_logic_vector(1 to 12);
    codeword: out std_logic_vector(1 to 24)
     );
end gencoder24;
 
architecture behave of gencoder24 is 
type matrix is array(1 to 144) of std_logic;
signal generato: matrix;
begin
 process(start,generato)
   variable ctr: integer;
   variable setbit,p:std_logic;
   begin
     if (start='1') then
     generato<=("011111111111111011100010110111000101101110001011111100010110111000101101110001011011100010110111100101101110101011011100110110111000101101110001"); --NON IDENTITY PART OF GENERATOR  
           
     ctr:=1;
     for j in 1 to 12 loop
       p:='0';
       for i in 1 to 12 loop
         setbit:=(insym(i) and generato(ctr));
         if (setbit='1') then
           p := not p; 
         end if;
         ctr := ctr+1;
       end loop;
       codeword(j+12)<=p ;
     end loop;
 
     for i in 1 to 12 loop
       codeword(i)<=insym(i); 
     end loop;
end if;
end process;
end behave; 
library ieee; 
use ieee.std_logic_1164.all;
 
entity inpbus24 is 
 port(i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,
    i15,i16,i17,i18,i19,i20,i21,i22,i23,i24:in std_logic;
    mx:out std_logic_vector(1 to 24)
   ); 
    
end inpbus24;
 
architecture behave of inpbus24 is 
begin
 mx(1)<=i1;
 mx(2)<=i2;
 mx(3)<=i3;
 mx(4)<=i4;
 mx(5)<=i5;
 mx(6)<=i6;
 mx(7)<=i7;
 mx(8)<=i8;
 mx(9)<=i9;
 mx(10)<=i10;
 mx(11)<=i11;
 mx(12)<=i12;
 mx(13)<=i13;
 mx(14)<=i14;
 mx(15)<=i15;
 mx(16)<=i16;
 mx(17)<=i17;
 mx(18)<=i18;
 mx(19)<=i19;
 mx(20)<=i20;
 mx(21)<=i21;
 mx(22)<=i22;
 mx(23)<=i23;
 mx(24)<=i24;
end behave; 
    
library ieee; 
use ieee.std_logic_1164.all;
 
entity gdtotal2 is 
port(rxsym: in std_logic_vector(1 to 24);
  s : out std_logic_vector(1 to 12);
  tns: out std_logic_vector(1 to 24);
  nsa:out std_logic
   );
end gdtotal2;
 
architecture behave of gdtotal2 is 
 
signal generato : std_logic_vector(1 to 144);      
           
signal e : std_logic_vector(1 to 24);
 
type bit12 is array(1 to 12) of std_logic;
 
begin 
 
process(rxsym)
variable ctr,wtctr:integer; --ctr TRACK OF GENERATOR MATRIX        
 
 
 variable setbit,p,ns:std_logic; -- TEMPORARY VARIABLES
 
variable syntemp:bit12; -- TEMPORARY 12-BIT VECTOR FOR SYNDROME
 
 
begin -- OF PROCESS ...
 --STEP 2 STARTS...
 
generato<=("011111111111111011100010110111000101101110001011111100010110111000101101110001011011100010110111100101101110101011011100110110111000101101110001");
 
 
 ctr:=1;
 
 for j in 1 to 12 loop 
   p:='0';
   for i in 13 to 24 loop
     setbit:=rxsym(i) and generato(ctr);
     if (setbit='1') then
p := not p;
     end if;
     ctr :=ctr+1;
   end loop;
   syntemp(j):=p;
 end loop;
 for i in 1 to 12 loop
   syntemp(i):=syntemp(i) xor rxsym(i);
   s(i)<=syntemp(i);
 end loop;-- END OF SYNDROME CALCULATION.  
 --STEP 2 ENDS.
 
 --STEP 3 STARTS...
 wtctr:=0;--CALCULATING WEIGHT OF SYNDROME...
 for i in 1 to 12 loop
   if(syntemp(i)='1') then
     wtctr:=wtctr+1;
   end if;
 end loop;
 
 if (wtctr<=3) then-- CHECKING CONDITION...
   ns:='0';
   for i in 1 to 12 loop --FIRST 12 BITS OF ERROR VECTOR  
   -- ASSIGNED THE SYNDROME.
     e(i)<=syntemp(i);
   end loop;
   for i in 13 to 24 loop--THE NEXT 12 ARE MADE 0.
     e(i)<='0';
   end loop;
   
 else--IF CHECK FAILS, ERROR VECTOR SET TO ZERO...
   for i in 1 to 24 loop
     e(i)<='0';
     
   end loop;
   ns:='1';
 end if;
 for i in 1 to 24 loop--XORING THE RECEIVED VECTOR WITH ERROR VECTOR
     tns(i)<= e(i) xor rxsym(i);
 end loop;
 nsa<=ns; --FLAG FOR ACTIVATING THE NEXT STEPS IN THE ALGORITHM.
 
end process;  
 
end behave;-- END OF ARCHITECTURE BEHAVE

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