OK. I will refraze my question.
I need function in vhdl or Verilog vith:
RegisterIN : IN std_logic_vector (7 downto0);
Numb1 : OUT std_logic_vector(3 downto 0);
Numb2 : OUT std_logic_vector(3 downto 0);
Numb3 : OUT std_logic_vector(3 downto 0);
IF RegisterIN is 10011001 --153 in Dec,
Numb1 must be 0001 -as 1 in dec
Numb2 must be 0101 -as 5 in dec
Numb3 must be 0011 -as 3 in dec
This is IT !!!!
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