Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Biasing conditiion of a MOS transistor

Status
Not open for further replies.

hannover90

Member level 4
Joined
Dec 8, 2009
Messages
70
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Germany
Activity points
1,784
Hello all,

I know about on- and off-conditions of a MOS transistor, but I don't know
what is "bias condition" of a MOS transistor.

I would be thankful if someone could explain it.
 

A MOSFET's bias condition describes it's (perhaps momentary) condition of conductivity, fixed by it's gate-source voltage Vgs: could be on or off, or a Vgs which stabilizes a certain impressed drain current Id, e.g. by the connection to the gate-source voltage of a current mirror.
 

When using a FET as a linear amplifier it is typically biased at some drain current level that places the drain voltage at about half the supply voltage through the drain-supply resistor.
Then the collector voltage can swing ± around this bias voltage when it is amplifying an AC input signal.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top