Biasing CMOS analog design

[chiragjain146]

Need help in generating Bias Voltage Vb( i.e. of 2nd pmos of cascode from top)

 

[shar2013]

I would create a pmos "flavour" from the left most branch

 

[chiragjain146]

I would create a pmos "flavour" from the left most branch

Sorry i didnt get you. some sort of image would be grateful

 

[kenambo]

Hi,

May i know the supply voltage ... and whats your output voltage?

And use the upper Pmos current source bias or use seperate leg if you want precise bias voltage.. It depends on you...

Thanks

 

[chiragjain146]

Hi,

May i know the supply voltage ... and whats your output voltage?

And use the upper Pmos current source bias or use seperate leg if you want precise bias voltage.. It depends on you...

Thanks

actually my qsn states that i need a high CMRR and high swing(2.2v)
supply is 3.3v... so a diode connected bias wont work

 

[erikl]

... supply is 3.3v... so a diode connected bias wont work

You could get your Vb from top of one of these sketched resistors:

 

[chiragjain146]

sry forgot to mention cant use resistors...
as of now i have done using a diode connected pmos(with a different W/L) and gave its gate volatge...
but the matching isnt perfect

 

[erikl]

sry forgot to mention cant use resistors...
as of now i have done using a diode connected pmos

Instead, try and use a (small) pmos with its gate connected to GND or to one of the n-bias voltages. Or an nmos with its gate connected to the upper p-bias voltage, or to VDD.

 

[skamthey]

i need a high CMRR and high swing(2.2v)
supply is 3.3v... so a diode connected bias wont work

Hi Chirag,
As u need good output swing, you can go with Low voltage Cascode Current Mirror circuit mention in Razavi.
One more point : In your circuit How You are generating gate bias for your PMOS tail current mirrors. It looks like your PMOS (diode connected 3rd branch) is off.