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Beta multiplier voltage reference

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analog_fever

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beta multiplier

I am a beginner to voltage reference design and I have a very basic
probably dumb question regarding low-power reference design discussed in
Jacob baker's book (figure shown).

In the book he explains that, for example, if Vreg
is greater than the the drain voltage of M1 (VbiasN), it
increases the output voltage of the opamp, which in turn
decreases the current through both M4 and M3 by the same amount
(because of symmetry).

Now the confusion I have is - Is not the opamp supposed to decrease
the difference between Vreg and VbiasN? How does it accomplish
this if reduces Vreg and VbiasN by the same amount? We want Vreg
and VbiasN to be equal for the reference to work, right?

I know that a good opamp tries to minimize its input offset, but
I am having trouble in understanding intuitively how the opamp
actually works in this circuit.
 

sutapanaki

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beta multiplier bias

Your confusion comes from the wrong assumption that Vreg and Vbiasn are reduced by the same amount. To help you understand, look at the attachment. Let's split the problem first and then look at the whole circuit.
Suppose you have just the NMOS part of the bias as I show in fig.1. M1 is diode connected and gets a current Io from a current source. M2 is biased by M1 and conducts some current I. Let's first suppose that both M1 and M2 have the same size W/L. The I-V characteristic of M1 is the familiar square law curve. For M2 this is not the case since it is degenerated by the resistor which makes it a bit more linear than M1. If we increase the voltage above the threshold Vth, initially for small currents the two curves almost overlap because the drop across R is insignificant. For bigger currents the two curves start to deviate.
Imagine now the situation when M2 size is 4x bigger as in Fig.2. Its V-I curve will be above that from fig.1 because for the same gate voltage M2 will conduct more current now. The curves for M1 and M2 intersect at some point which correspond to the same amount of current in both M1 and M2. Suppose that now we decrease the current in M1 to Io1. This will develop a gate voltage for M1 equal to Vg1. This gate voltage will cause some current in M2 and it is obvious from the graph that M2's current will be bigger than that of M1 - point A. If, instead we increase the current in M1 to Io2, this will force a current in M2 that is smaller than Io2 - point B.
Now back to the bias circuit. If Vreg is bigger than VbiasN, the opamp will make the gates of the PMOS current sources higher and their current will decrease. The current of those PMOS current sources is the current going into M1. According to fig.2, this decreased current will force a current in M2 that is bigger than the current in M1 which is equal to the current in M3 and equal to the current M4 is trying to force. However, the drain of M4 and the drain of M2 meet at a high impedance point and fight against each other. Since the current M2 is trying to impose is bigger than the current M3 is trying to force, the voltage Vreg will decrease. The circuit will find its balance point when the current of M2 becomes equal to the current of M4. The opamp will be happy since the two inputs will be mostly equal.
 

snafflekid

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how does beta multiplier current reference works

A simple handwaving explanation is if you had only the bottom half (M1 and M2) and swept the gate voltage, M1 drain current and M2 drain current would be different.

M1 and M2 have different gm, and M2 has source degeneration resistor. So the gain on the left side is higher than on the right side. For high gate voltages, M1 pulls down harder.

This increases the op amp input voltage, raises the pmos gate voltage and drops the two currents equally. This current drops to a point where the currents equal.
 

analog_fever

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beta multiplier circuit

sutapanaki and snafflekid,

thanks a bunch for taking time to provide the explanation. I will get back if I have any questions.
 

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