pbernardi
Full Member level 3
Hello,
I would like to decode a table of bits into register according predeterminated conditions:
a) we have a input of n bits (Typical 16, 32 or 64 bits)
b) Some of these bits are or condition bits, and determines what others bits mean, and to with register they should go.
c) If a register is not decoded, it must be set to 0.
I think the best way to explain is by example, it is the best I could do until now (in Verilog):
The problem with this approach is that if we have a lot of registers and lots of decoding (it is my case), the coding has still some complexity (altough much better that a if/else for each register). I would like to simplify more and wonder if there is some way to avoid the "<= 0" attribution on each if, in order to keep the code easy to mantain.
Verilog is my natural hardware language, but suggestions in VHDL are also welcome. Any suggestions?
I would like to decode a table of bits into register according predeterminated conditions:
a) we have a input of n bits (Typical 16, 32 or 64 bits)
b) Some of these bits are or condition bits, and determines what others bits mean, and to with register they should go.
c) If a register is not decoded, it must be set to 0.
I think the best way to explain is by example, it is the best I could do until now (in Verilog):
Code:
reg A, B;
reg [1:0] C;
reg [2:0] D;
reg [3:0] E;
reg [7:0] input;
always@(posedge CLK)
begin
if (input [1:0] == 2´b00) begin {E,C} <= input[7:2]; {A, B, D} <= 0; end else
if (input [1:0] == 2´b01) begin {A,D,C} <= input[7:2]; {B, E} <= 0; end else
if (input [1:0] == 2´b10) begin {A,B,E} <= input[7:2]; {D, C} <= 0; end else
if (input [1:0] == 2´b11) begin {B,C,D} <= input[7:2]; {A, E} <= 0; end
end
The problem with this approach is that if we have a lot of registers and lots of decoding (it is my case), the coding has still some complexity (altough much better that a if/else for each register). I would like to simplify more and wonder if there is some way to avoid the "<= 0" attribution on each if, in order to keep the code easy to mantain.
Verilog is my natural hardware language, but suggestions in VHDL are also welcome. Any suggestions?