shaiko
Advanced Member level 5
Benefits of using virtual clocks in SDR interfaces
Suppose I have a simple SDR source synchronous interface sending data + clock to my FPGA.
The timing relationship between the data and clock are known - so I can proceed with constraining the input pins of my FPGA with reference to that real clock.
However, many examples recommend constraining the input relatively to a "virtual clock".
They define a virtual clock that's 100% identical to the real clock and proceed with setting input delays in reference to it.
Non of the explanations I read so far explains the benefits of this practice in a clear manner...
Can you please explain the benefits ?
Suppose I have a simple SDR source synchronous interface sending data + clock to my FPGA.
The timing relationship between the data and clock are known - so I can proceed with constraining the input pins of my FPGA with reference to that real clock.
However, many examples recommend constraining the input relatively to a "virtual clock".
They define a virtual clock that's 100% identical to the real clock and proceed with setting input delays in reference to it.
Non of the explanations I read so far explains the benefits of this practice in a clear manner...
Can you please explain the benefits ?