To my experience with generations about 0.25um & 0.18um fab,
It is not process issue;
See under modern CMP (chemical mechanical polish) technology,
they fine polish after each inter-metal oxide layers.
And MiM cap resides below last metal (top floor), which is more than 4um
away from silicon surface. And after more than 4 times of CMP, it's real flat up there.
Plus the thickness of the MiM dielectric ayer is fabricated by chemical deposition,
the control factor is time (~10sec).
I don't think a 4um away 0.1um~0.2um thick poly gate can affect it's capacitance after 4 CMP.
The real problem here is about modeling ( or parasitic couling...) or simulation,
foundry do not believe they can properly model what is really happening electrically,
and then presim and postsim could fail.
Integrated circuit business is such a big business,
that they should rule out any possible risk as much as they can...