Jun 12, 2012 #1 V venugopala_0202 Junior Member level 1 Joined Apr 23, 2012 Messages 19 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,422 Hello Recently I attended an interview. The following was one of the questions that were asked- A module has two inputs, clk and reset. Write a verilog code to suppress the even pulses of the clock. Could someone here post a verilog code to do this?
Hello Recently I attended an interview. The following was one of the questions that were asked- A module has two inputs, clk and reset. Write a verilog code to suppress the even pulses of the clock. Could someone here post a verilog code to do this?
Jun 12, 2012 #2 M morris_mano Full Member level 2 Joined Apr 9, 2012 Messages 137 Helped 39 Reputation 78 Reaction score 41 Trophy points 1,308 Location US Activity points 2,774 This is frequency divide by 2 question without 50% duty cycle. One way to do is Code: module divby2( input clk, input reset, output div_clk); reg div_clk_q; wire div_clk_d; always @ ( posedge clk, negedge reset) begin: clk process if(!reset) begin div_clk_q <= 1'b0; end else begin div_clk_q <= div_clk_d; end end assign div_clk_d = ~div_clk_q; assign div_clk = div_clk_q & clk; endmodule Assumption, active low reset.
This is frequency divide by 2 question without 50% duty cycle. One way to do is Code: module divby2( input clk, input reset, output div_clk); reg div_clk_q; wire div_clk_d; always @ ( posedge clk, negedge reset) begin: clk process if(!reset) begin div_clk_q <= 1'b0; end else begin div_clk_q <= div_clk_d; end end assign div_clk_d = ~div_clk_q; assign div_clk = div_clk_q & clk; endmodule Assumption, active low reset.