Apr 19, 2015 #1 T tv123 Junior Member level 3 Joined Mar 16, 2015 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 162 Will the power consumption for a design done in behavioral verilog and structural verilog be same?
Apr 19, 2015 #2 S sharath666 Advanced Member level 2 Joined Apr 4, 2011 Messages 552 Helped 126 Reputation 252 Reaction score 124 Trophy points 1,323 Location India Activity points 3,830 If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.
If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.
Apr 19, 2015 #3 T tv123 Junior Member level 3 Joined Mar 16, 2015 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 162 sharath666 said: If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different. Click to expand... What if both refers to same logic, say , if both refer to a d flipflop?
sharath666 said: If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different. Click to expand... What if both refers to same logic, say , if both refer to a d flipflop?
Apr 19, 2015 #4 S sharath666 Advanced Member level 2 Joined Apr 4, 2011 Messages 552 Helped 126 Reputation 252 Reaction score 124 Trophy points 1,323 Location India Activity points 3,830 Then it should be the same as post synthesis netlist will be the same.