Behavioral and structural modelling in verilog

[tv123]

Will the power consumption for a design done in behavioral verilog and structural verilog be same?

 

[sharath666]

If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.

 

[tv123]

If your behavioral code infers a different logic when compared to your structural verilog code, then the power consumed will be different.

What if both refers to same logic, say , if both refer to a d flipflop?

 

[sharath666]

Then it should be the same as post synthesis netlist will be the same.