The FF discussion was about achieving a low jitter start of conversion signal, but you didn't tell about your jitter requierements, in so far it's a purely theoretical discussion up to now.
The other point is the decoding of serialized data. I see two options with Arria FPGA:
- Using SERDES in logic cells, driven by DCO, no receiver PLL. A simple, straightforward method.
- Using Arria dedicated hardware SERDES, which is always driven by a PLL. Arria can do this with a single PLL for 8 ADCs, if the internal clock is used rather than DCO. DPA functionality with the specific ADC frame must be checked, I guess, it can still work.
For the connector, any standard with an differential impedance around 100 ohm can work. For short distance even a standard 0.1" pin header with IDC cable.