Hi, can anyone give me some good references/links/books for information on designing systems that consist of a CPU core, with functionality implemented around the CPU (such as ethernet controller, hard disc controller), that are implemented on an FPGA.
I am unsure of the number of macrocells a typical FPGA has, and the macrocells required to implement an 8051 core. How would you go about developing software for the 8051 core?
There you will find the 3 parts serie of articles from CircuitCellars:
"Building a RISC System in an FPGA"
Part 1: Tools, Instruction Set, and Datapath
Part 2: Pipeline and Control Unit Design
Part 3: System-on-a-Chip Design
BTW, usually definition "macrocell" is used for CPLD, FPGA's logic block is referred as a CLB (Configurable Logic Block).
You can try "Nios". This is a "soft" 16/32bit CPU developed by @ltera. It only need 1000-2000 LE.
The most important thing is: It has enough documents,software tools ,
and it is fully tested. Of course,MicroBlaze,a soft CPU from Xilinx, is another good choice.
I don't suggest you to use those free CPU core if you have a real project to do.