Li-Ion battery model in verilog-A
Hey ppl.
Im posting here the behavioral model that I made using verilog-A on a cadence environment. Whoever is working with battery management circuits and charge/recharge simulations might find it useful.
Test it and trim it if you can, because sometimes it creates unstabilties in the circuits because of odd operating points calculations. I didnt do the voltage limiting on the model but I think one of you can do it... if not I will do it... but later.
The default model is a 850 mAh Li-Ion battery model. The state of charge is easily settable with the soc parameter (0 = 0%, 1=100% of charge). The capacity is defined by the Ccharge parameter, which is 3060F for a 850 mAh battery. Dont mess with the other parameters unless you know what youre doing.
Enjoy =)
//Verilog-AMS HDL for <library_name>, <modelname> <cellview>
`include "constants.vams"
`include "disciplines.vams"
module <modelname>(gnd, nsoc, vbat);
inout gnd, nsoc, vbat; // i/o pins
electrical gnd, nsoc, vbat; // main nodes
electrical n0, n1, n2; // internal nodes
electrical n1n2, n2vbat; // dummy nodes for calculations
parameter real Rdischarge=1M, Ccharge=3060; // parameters for the charge model part
parameter real Ra=0.07446, Rb=0.04669, Rc=0.04984; // Parameters for the internal dynamic resistances
parameter real Cb=703.6, Cc=4475; // Parameters for the internal dynamic capacitances
parameter real soc=1;
analog begin
// ***DEFINITION OF THE BATTERY LIFETIME CIRCUIT*** //
@(initial_step)
V(nsoc,gnd) <+ soc;
// internal current controlled current source
I(nsoc,gnd) <+ I(gnd,n0);
I(nsoc,gnd) <+ V(nsoc,gnd)/Rdischarge;
I(nsoc,gnd) <+ Ccharge*ddt(V(nsoc,gnd));
//**************************************************//
// ***DEFINITION OF THE TRANSIENT RESPONSE OF THE BATTERY*** //
// Voltage controlled voltage source
V(n0,gnd) <+ 3.685-1.031*exp(-35*(V(nsoc,gnd)))+0.2156*(V(nsoc,gnd))-0.1178*pow(V(nsoc,gnd),2)+0.3201*pow(V(nsoc,gnd),3);
// Series resistance
V(n0,n1) <+ I(n0,n1)*(Ra+0.1562*exp(-24.37*(V(nsoc,gnd))));
// Fast transient RC network
I(n1n2) <+ ddt(V(n1,n2));
V(n1n2,gnd) <+ I(n1n2)*0.1*Rdischarge;
I(n1,n2) <+ V(n1,n2)/(Rb+0.3208*exp(-29.14*(V(nsoc,gnd))));
I(n1,n2) <+ (Cb-752.9*exp(-13.51*(V(nsoc,gnd))))*I(n1n2);
// Slow transient RC network
I(n2vbat) <+ ddt(V(n2,vbat));
V(n2vbat,gnd) <+ I(n2vbat)*0.1*Rdischarge;
I(n2,vbat) <+ V(n2,vbat)/(Rc+6.603*exp(-155.2*(V(nsoc,gnd))));
I(n2,vbat) <+ (Cc-6056*exp(-27.12*(V(nsoc,gnd))))*I(n2vbat);
end
endmodule