BASIC VHDL problem!Please help!

[Yoking]

Im now learning VHDL,but i encounter an embarrassed problem: i cant simulate this simple VHDL code with modelsim6.0 properly.Please help me out,thanks.

VHDL CODE:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;


entity frediv is
port(
clk:in std_logic;
en:in std_logic;
qoutut std_logic
);
end frediv;

architecture behave of frediv is
signal mid1: std_logic;
begin
process(clk)
--variable mid1: std_logic;
begin
if clk'event and clk='1' then
if en='1' then
mid1<= not mid1;
end if;
end if;
end process;
qout<=mid1;
end behave;

Testbench CODE:

library IEEE;
use IEEE.std_logic_1164.all;

entity TB_FREDIV is
end TB_FREDIV;

architecture BEH of TB_FREDIV is

component FREDIV
port(CLK : in std_logic ;
EN : in std_logic ;
QOUT : out std_logic );

end component;


constant PERIOD : time := 10 ns;

signal W_CLK : std_logic := '0';
signal W_EN : std_logic ;
signal W_QOUT : std_logic ;

begin

DUT : FREDIV
port map(CLK => W_CLK,
EN => W_EN,
QOUT => W_QOUT);

W_CLK <= not W_CLK after PERIOD/2;

STIMULI : process
begin
W_EN <= '1';

wait for PERIOD;
-- wait;
end process STIMULI;

end BEH;

configuration CFG_TB_FREDIV of TB_FREDIV is
for BEH
end for;
end CFG_TB_FREDIV;

 

[lordsathish]

Hi...
where do you get a error...?
I think your code should compile properly...
there could be syntax errors in your test bench i guess...
Its been long time since i used vhdl...
I'm not sure if it is case sensitive...?

 

[angelote]

You have to giave an initial value for mid1.

For example:
signal mid1: std_logic := '0';

I'd better use a reset signal that really sets that initial value for mid1 into the process.

In real world, that would work, but if you don't give an initial value for mid1, ModelSim doesn't know where to start from.

 

[Yoking]

Thanks angelote!
That works ok!