1- the goal of a synthesis tools is to tranform RTL in netlist, so the tools require as input at minimum a and and flop. The elaboration step is only a first stage and do not need any stdcell.
2- tools could replace flops with constant input, stuck value, reorganise the pipeline..
3- see responce provided by mail4idle2
4- what do you mean by detected by the circuit? if any of these violation occurs on the real chip, the functional behavior will not any more guarantee. STA is here to check that.
5- see previous responce.