Basic Question regarding sub-module place and route

[mxm1234]

Hello all,
I am trying to do the following:

• 
  I have .saif file generated from RTL simulation of the OpenSPARC T1 core (from regression suite). I also have the whole design synthesized (GATE LEVEL) with SAED_90nm library.

• 
  Right now I am only interested in the ALU unit of the design. So, I generated the .saif file (from RTL Simulation) which contains the switching activity for just the ALU unit from the whole core. I read the synthesized ALU design with clock and the .saif (read_saif) file in design vision to generate the power.

• 
  Next I wanted to verify the power number reported by design vision by simply place and route (Cadence SOC Encounted) the ALU unit to generate .sdf and place and routed netlist. I am planning to use the same .saif file generated from RTL simulation.

My question is:

• 
  When I try to place and route the just the ALU unit to generate the .sdf and placed&routed netlist, do I need to "add floorplan", define VDD/VSS, add the power rings around the ALU, add stripes, then do the Clock Tree Synthesis (CTS) and route the standard cells?
  When I go through this procedure, in Verify Geometry and Verify Connectivity (after detailed routing) I have a lot of "Spacing", "Wiring", "Open" and "Short" errors.

• 
  Or, I could simply place the standard cells, do CTS, and detailed Route the design to generate the netlist and sdf?

I do not plan to tape out, so don't think LVS is necessary for me. I am new to this process, and thus maybe this basic question.

Also, how do i generate the .saif from gate level simulation. The regression suites in OpenSPARC T1 is defined in Assembly language and it uses midas (Assembler) to genreate the memory image (I guess) and then uses VCS to simulate. In the top level testbench there is a way to define the vcd_dump command. Thats how I was generating the VCD from RTL Simulation.

Please Help.

 

[ThisIsNotSam]

you don't need the stripes or power rings, but you will still need to define special nets and do special route.

I don't understand why you would see violations with connectivity checks. go over your logs, something is wrong.

 

[mxm1234]

when I don't add the power rings or add "Floorplan" after importing the design, simply using Place Standard Cell and then Detailed route does not yield any Connectivity Violation. There are some Geometry Violation (mostly Minimum space error and Minimum WIDTH error), but I think it is because of the .lef file "VIA" definition. The VIAs are larger than the Metal layer on one side.

But I want to understand the part where you mentioned I don't need Stripes/Power Rings for what i am trying to do, but do "Special Route"? When I tried "sroute" after placing (planning) Power rings and stripes, it threw error:

    332 Reading LEF technology information...
    333 Reading floorplan and netlist information...
    334 Finished reading floorplan and netlist information.
    335    **WARN: width of LAYER M2 of VIA VIA12B less than minimum width
    336    **WARN: width of LAYER M9 of VIA VIA89 less than minimum width
    337    **WARN: width of LAYER M7 of VIA VIA78 less than minimum width
    338    **WARN: width of LAYER M8 of VIA VIA78 less than minimum width
    339    **WARN: width of LAYER M6 of VIA VIA67 less than minimum width
    340    **WARN: width of LAYER M7 of VIA VIA67 less than minimum width
    341    **WARN: width of LAYER M5 of VIA VIA56 less than minimum width
    342    **WARN: width of LAYER M6 of VIA VIA56 less than minimum width
    343    **WARN: width of LAYER M4 of VIA VIA45 less than minimum width
    344    **WARN: width of LAYER M5 of VIA VIA45 less than minimum width
    345    **WARN: width of LAYER M3 of VIA VIA34 less than minimum width
    346    **WARN: width of LAYER M4 of VIA VIA34 less than minimum width
    347    **WARN: width of LAYER M2 of VIA VIA23 less than minimum width
    348    **WARN: width of LAYER M3 of VIA VIA23 less than minimum width
    349    **WARN: width of LAYER M2 of VIA VIA12A less than minimum width
    350    *ERROR* LAYER M1, THICKNESS is required for ANTENNA side area computation
    351    *ERROR* LAYER M2, THICKNESS is required for ANTENNA side area computation
    352    *ERROR* LAYER M3, THICKNESS is required for ANTENNA side area computation
    353    *ERROR* LAYER M4, THICKNESS is required for ANTENNA side area computation
    354    *ERROR* LAYER M5, THICKNESS is required for ANTENNA side area computation
    355    *ERROR* LAYER M6, THICKNESS is required for ANTENNA side area computation
    356    *ERROR* LAYER M7, THICKNESS is required for ANTENNA side area computation
    357    *ERROR* LAYER M8, THICKNESS is required for ANTENNA side area computation
    358    *ERROR* LAYER M9, THICKNESS is required for ANTENNA side area computation
    359    A total of 9 errors and 15 warnings.

and after running the "Verify Connectivity" (Post CTS and Detailed route):

Snippets of ALU.conn.rpt:

Net VDD, Pin U2367.VDD: unconnected terminal at (180.160000,10.160000) (182.080000,10.320000)
Net VDD: special open at (164.480000,10.160000) (179.200000,11.625000)
.......

246 Begin Summary
247     58 Problem(s) [ 96]: Terminal(s) are not connected.
248     178 Problem(s) [200]: Special Wires: Pieces of the net are not connected together.
249     236 total info(s) created.
250 End Summary