Hi Princerock,
When you measure the ro of the NMOS, the drain of the NMOS you give dc value (sweep) without any load (RL) connected to the drain. This is only to find the effect of ro or λ of the NMOS. Then when it comes for the gain calculation for a simple CS amplifier, the gain is gmRL, where teh effect of ro is ignored as ro||RL, and is effect the RL as the load. You can use as simple CS stage to test out this effect.
As we know that, L ≈ 1/λ, since your L size is big, the effect of λ could be lesser. That's why in the differential amplifier design, normally we see set the value of L to be 2 or 3 x than effective length of the tail transistor to minimize the effect of λ as the total gain of the diffamp is controlled by the switching current at the tail.
Well, to find out the gain of your CS amplifier, u give the dc voltage and AC=1 at the gate of NMOS or PMOS with load RL connected at the drain. Then you plot the Vout/Vin and scale it in logaritmic. I'm sure you will see the gain of your circuit in db.
Hereby i'm attaching 2 papers which will help you on the simulation.
Regards,
Suria3