In Saturation, the channel region is pinched off well before the drain. then how does current get from source to drain resulting in large drain current.?
In Saturation, the channel region is pinched off well before the drain. then how does current get from source to drain resulting in large drain current.?
Thanks,
At first, your question is related to FET properties in general - not specifacally to CMOS.
At second, "saturation" does not mean that the "door is closed". Instead it decribes something like an equilibrium between energy resp. velocity of the carriers (electrons or holes) and the channel width which in turn becomes smaller when the drain-source voltage (and with it the carrier velocity) rises.
In saturation, its a constant Current rather than interpreting as the max drain current. Bcoz the value of Ids can also be varied by changing the Gate voltage!!
Hope u can recollect the Ids Vs. Vds graps ( for various values of Vgs)
One correction...
In saturation, its a constant Current rather than interpreting as the max drain current. Bcoz the value of Ids can also be varied by changing the Gate voltage!!
Hope u can recollect the Ids Vs. Vds graps ( for various values of Vgs)
In saturation, the current is NOT constant (the Id-Vds curve has a positive slope !).
This effect leads to the well known EARLY voltage (originally defined for BJTs and later adopted to FETs).