swagata
Member level 3
i am designing a current conveyor........a modified current mirror.i notice that as the input output linearity error decreases while the transient response gets worse.
i have .35u technology and i have chosen L=.5um . The width is below 3um for NMOS.
Analog designers are requested to comment on my device sizing and how i can improve the transient response. i have not much idea on matching problems at layout level in practical. So please let me know how can i improve my design.
thnx in advance
swagata
i have .35u technology and i have chosen L=.5um . The width is below 3um for NMOS.
Analog designers are requested to comment on my device sizing and how i can improve the transient response. i have not much idea on matching problems at layout level in practical. So please let me know how can i improve my design.
thnx in advance
swagata