Bandgap voltage Reference ac test schematic question

[neter]

gain phase margin voltage reference test setup

Hi,I will design High PSRR Low power bandgap voltage reference,but i don't know
stability test (AC) circuit whether test schematic is right or not in gif files.

How can design stability test schematic in this bandgap?(ex: look for phase margin? UGB?)

thanks a lot.

 

[neter]

bandgap ac

Hi,I upload the clear test schematic,i have does a stability analysis in this bandgap circuit. but, i can't sure whether my inject ac source point is right or not.

 

[pfd001]

bandgap transient response

your inject ac source is correct

 

[butterfish]

bandgap voltage

I am not clear, why do you add two ac source in one loop?

 

[kivvzhou]

voltage bandgap schematic

The AC test circuit is right ,I think !The you can see the point the LAC2 (the right of N2 )the phase margin and gain bandwidth (usually 0.1meg ~1meg)

 

[neter]

ac voltage reference

Dear all,

Thanks a lot.

 

[youyang]

bangap schematic

Dear all,

Thanks a lot.

hi

I just wonder what's the function of transistor Mc1 and Mc2?

thanks

 

[jwfan]

ac simulation setup for bandgap voltage reference

Used as a capacitor

Dear all,

Thanks a lot.

hi

I just wonder what's the function of transistor Mc1 and Mc2?

thanks

 

[youyang]

how to test the bandgap voltage?

Used as a capacitor

hi jwfan

Then, what is the difference of making a capacitor between using a real capacitor and a MOS transistor?

 

[haoshs]

ac reference schematic

The capacitance of MOS cap is usualy larger than that of PIP.
however, it charge with voltage applyed to the cap.

 

[No8]

gain phase margin voltage reference test setup

Thanks for you informaion.
I'll study it.

 

[JT]

schematic voltage reference

I don't agree with your simulation schematic.

You are correct to cut both the loops of the opamp, but where will you look at your fed back signal (for phase analyis )?

The way I usually do it is cut at the output of the amp, then you've got both loops in one shot !

Don't forget to copy the output load of the opamp.

Good luck, J

 

[jwfan]

schemat bandgap

Then, what is the difference of making a capacitor between using a real capacitor and a MOS transistor?

If the process has double poly layer, then, Use poly-poly2 capacitor is good. But if not, than the mos tansistor capacitor is better than the poly-metal or metal1-ploy-metal2 capacitor.

 

[ipsc]

Hi,

I don't think the setup is right.

Under DC conditions the AC source is shorted to Emitter of Q1. I think, this will affect the operating point of system, even if the DC voltage of AC source is kept as '0'V.

Regards
--ipsc

 

[hrkhari]

Hi Guys:

I often come across in situation of determining the transient stability in BGR design as a requirement. Since the ac stability analysis only potray the small signal analysis.

Usually a Vpwl is applied to the Vdd to be ramped from 0v to Vdd, and the output is cross checked whether it settles down at the desired value, correct me if I'm wrong?. Is it the input or the Vdd is ramped. Thanks in advance

Rgds

 

[ipsc]

Hi Guys:

I often come across in situation of determining the transient stability in BGR design as a requirement. Since the ac stability analysis only potray the small signal analysis.

Usually a Vpwl is applied to the Vdd to be ramped from 0v to Vdd, and the output is cross checked whether it settles down at the desired value, correct me if I'm wrong?. Is it the input or the Vdd is ramped. Thanks in advance

Rgds

Yes, I do agree with you that transient analyisis is the ultimate test of stability. If you get good transient response it's ok. But what if your transient analysis is bad, say, it has lot of damping etc. I mean, how will you solve this problem?

AC analysis and Phase Margin helps you here. Agreed, good Phase Margin doesn't necessarily mean good transient response. But good AC response generally does. Here, by good AC response I mean good Phase Margin, along with no zeros @UGB etc.

To cut short, Transient tells about system's stability and AC response gives control over it.

Besides AC response gives DC gain. More the gain, lower is the closed loop systematic offest. For Bandgap we need low offset.

These are my thoughts. Point me, if i am wrong.

Is it the input or the Vdd is ramped.

For bandgap it's VDD.

Regards