If possible, you would like a few samples of a PCM test coupon,
a modeling test vehicle, something with the device you mean to
use. Then you take data (Gummel, and ideally some in the bias
condition you plan to use since Gummel is a not-useful circuit
configuration) that you can turn into things like a transdiode
log I-V (useful to assess the linearity of the real diode I-V
across decades of range, which is essential to the bandgap's
PTAT ideality) and beta-vs-IC with VCE=VBE (one way the
diode will slide off from expected - the beta is what idealizes
the transdiode and strongly influences the "Vf" (much lower
than the plain drain-well junction will read, because collector
current is most of the "diode" current).
You are interested in how real data (off a semiconductor
parameter analyzer like HP4145, 4156, ...) compares to
what the CAD system coughs up. And particularly at small
device sizes, periphery effects can make this vary a lot.
The base (well) surface in a CMOS process has only to "not
invert", as far as the process guys know or care. But if you
use it as a BJT, if it even moves a bit toward depletion then
the surface region takes more of Ib and then loses it to
surface recombination, killing low current beta and raising Vf
away from the ideal line. You might have need of field plating
to make it bend the right way, all that kind of thing. You might
want a "walled base" to force current flow vertical, despise
that this hurts Rc (by added distance) and device size. And so
on. On a "freebie" device like this, groundrules may be "what
will print" more than "what is best".
This is what you want to know. How much to believe the CAD
results. Because the final exam is a much more expensive
place to learn the lesson.
Even when you own the foundry, you may not "own" the agenda
of the modeling group. I know designers who have had to make
their own veriloga models for bandgap diodes, because they see
errors and can't get them fixed, even with data in hand. I have
borrowed their models because they work right and the "released"
models don't.
In any case you should begin with your foundry's application or
customer engineering folks. You may be the 37th guy to ask the
question and it merely never got pushed into the PDK docs /
models. Or maybe you are the first, and get to discover
something. Lucky you.
If you are a real customer with a real PO and a NDA in place,
there should be no problem getting you samples off some batch
of unshippable (hopefully for a reason unrelated to your interests)
wafers. Work the system.