Bandgap core - npn or pnp based?

[diarmuid]

Hello,

I have started using a bandgap with npn based core and have the following questions:

1. Is the pnp based core the more conventional?
2. Which core has better performance pnp or npn?
3. Does one core exhibit a lower 2nd order temperature dependance over the other? Does
npn exhibit a less severe temp curvature over pnp?

I guess one advantage of npn is it gives the possibility of substrate isolation but I cannot
think of any others.

Thanks,

Diarmuid

 

[FvM]

The question refers to the specific properties of an IC technology, but no technology has been mentioned.

In classical standard planar process, only NPN transistors have good performance.

 

[dick_freebird]

Given a choice I'd pick NPN because they almost
always have better hFE and parasitic resistances
even in complementary vertical bipolar flows.

In cheap common JI technologies the choice is
liable to be opportunistic and the topology, or
specific application of the device, constrained.
For example you may have the outstanding choices
of either a substrate PNP (collector is pinned hard
to substrate / GND, so only useful as a transdiode)
or an even more poorly modeled and controlled,
possibly not even recognized, lateral NPN.

If you have all three terminals free, a PNP core can
be useful for negative references (VDD-VBG).

 

[diarmuid]

Given a choice I'd pick NPN because they almost
always have better hFE and parasitic resistances
.

What is hFE?

I have heard that package stress affects npn's temp co more than pnp's.

Have you experienced this?

 

[Dominik Przyborowski]

hFE is the same as beta.

in fact in many CMOS processes only one type of BJT is available, e.g. vertical pnp.

 

[diarmuid]

in fact in many CMOS processes only one type of BJT is available, e.g. vertical pnp.

Do you mean that you require a triple well process do implement a vertical npn?

Could you not implement a lateral npn in a standard non-triple well process?

- - - Updated - - -

Is my understanding correct here:

In a standard non-triple well CMOS process (no DNW) you can achieve
- lateral npn (no substrate isolation)
- lateral pnp (substrate isolation)
- vertical pnp (no substrate isolation)

In a triple well CMOS process you can achieve
- lateral npn (substrate isolation)
- vertical npn (substrate isolation)
- lateral pnp (substrate isolation)
- vertical pnp (no substrate isolation)

Therefore both npn / pnp based cores can give me substrate isolation?

Is there a preference then with vertical vs lateral?

Thanks,

- - - Updated - - -

I guess all my questions have been answered with this lovely post:

https://www.edaboard.com/threads/58306/

Basically what Im seeing from this is laterals **** and verticals rule!

So in a standard CMOS process I cant make any vertical pnps with substrate isolation
whereas in a triple well process I can only make a vertical npn with substrate isolation.

So if Im looking for substrate isolation, I need a TW process and npn based core!